Examples of a memory embedded in a large scale integrated circuit (LSI) include a semiconductor memory device such as a static random access memory (SRAM). Examples of an SRAM includes a 1-read 1-write (1R1W)-SRAM, a 2-read 1-write (2R1W)-SRAM, and so forth in terms of configuration of a read port and a write port.
FIG. 1 is a diagram illustrating a configuration of an example of a 2R1W-SRAM. In FIG. 1, BL_0L, BL_0R, BL_1L, and BL_1R denote bit lines. In FIG. 1, WL_0L, WL_0R, W_1L, and W_1R denote word lines. In FIGS. 1, 1-00, 1-01, 1-10, and 1-11 (MC00, MC01, MC10, and MC11) denote memory cells that are provided in a memory cell array 1. In FIG. 1, 2-0L, 2-0R, 2-1L, and 2-1R are word line drivers that drive the word lines WL_0L, WL_0R, W_1L, and W_1R, respectively. In FIG. 1, only the four memory cells 1-00, 1-01, 1-10, and 1-11 provided in the memory cell array 1 are illustrated for simplicity of description. Two word lines WL_xL and WL_xR and two bit lines BL_xL and BL_xR are connected to each memory cell MC. For example, the two word lines WL_0L and WL_0R and the two bit lines BL_0L and BL_0R are connected to the memory cell 1-00. The word line drivers 2-0L, 2-0R, 2-1L, and 2-1R have the same configuration and the same occupied area.
FIG. 2 is a diagram illustrating a configuration of the memory cell 1-00 illustrated in FIG. 1. In FIG. 2, Vdd denotes a power-supply voltage, and Vss denotes the ground voltage. The other memory cells 1-01, 1-10, and 1-11 have the same configuration of the memory cell 1-00. The memory cell 1-00 has six transistors Tr1 to Tr6.
FIG. 3 is a diagram illustrating a configuration of an example of a 1R1W-SRAM. In FIG. 3, BL_0L, BL_0R, B_1L, and BL_1R denote bit lines. In FIG. 3, WL_0 and W_1 denote word lines. In FIGS. 3, 11-00, 11-01, 11-10, and 11-11 (MC00, MC01, MC10, and MC11) denote memory cells that are provided in a memory-cell array 11. In FIGS. 3, 12-0 and 12-1 are word line drivers that drive the word lines WL_0 and WL_1, respectively. In FIG. 3, only the four memory cells 11-00, 11-01, 11-10, and 11-11 provided in the memory-cell array 11 are illustrated for simplicity of description. One word line WL_x and two bit lines BL_xL and BL_xR are connected to each memory cell MC. For example, the one word lines WL_0 and the two bit lines BL_0L and BL_0R are connected to the memory cell 11-00. The word line drivers 12-0 and 12-1 have the same configuration and the same occupied area.
FIG. 4 is a diagram illustrating a configuration of the memory cell 11-00 illustrated in FIG. 3. In FIG. 4, Vdd denotes a power-supply voltage, and Vss denotes the ground voltage. The other memory cells 11-01, 11-10, and 11-11 have the same configuration of the memory cell 11-00. The memory cell 11-00 has six transistors Tr11 to Tr16.
The memory cell 1-00 illustrated in FIG. 2 has the same configuration of the memory cell 11-00 illustrated in FIG. 4. A cell area occupied by the memory cell 1-00 is the same as a cell area occupied by the memory cell 11-00. A read operation is performed by accessing the memory cell 1-00 using a pair of one word line and one bit line. In a 2-read operation, two word lines and two bit lines are used. In a 1-read operation, one word line and one bit line are used. When the 1-read operation is performed for the memory cell 1-00 illustrated in FIG. 2, only the capacitance of one transfer gate (Tr5 or Tr6) of the memory cell 1-00 influences the word line (WL_0L or WL_0R) as a load imposed thereon. Thus, when the 2R1W-SRAM illustrated in FIG. 1 operates as an SRAM that performs the 1-read operation, the power consumption of the 2R1W-SRAM in a case of the 1-read operation may be reduced, compared with the power consumption of the 1R1W-SRAM illustrated in FIG. 3 in a case of the 1-read operation. The occupied area of the word line drivers 2-0L and 2-0R that drive the word lines may be reduced, compared with that of the word line driver 12-0 illustrated in FIG. 3.
In order to increase a speed at which an operation of an SRAM having a configuration such as the configuration illustrated in FIGS. 1 and 2 is performed, in particular, in order to increase a speed at which a read operation of the SRAM is performed, it is desirable to sharply increase the potential of word lines. Accordingly, in order to sharply increase the potential of word lines, it is desirable to increase the physical size of word line drivers or to reduce a load imposed on each of the word line drivers by dividing a memory-cell array. Even when either the physical size of word line drivers is increased or a load imposed on each of the work-line drivers is reduced, the area of the entire SRAM is increased, and the power consumption of the SRAM is increased.
It is desirable for the semiconductor memory device of the related art to realize a high-speed operation without causing the occupied area of a driver section to be increased or causing the power consumption of the entire semiconductor memory device to be increased.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2006-269023    [Patent Document 2] Japanese Laid-open Patent Publication No. 5-218354    [Patent Document 3] Japanese Laid-open Patent Publication No. 6-295588